1. Field of the Invention
This invention relates to the field of bus bridge integrated circuits and in particular to a bus bridge circuit design that includes registers to store configuration parameters pertaining to upstream memory operations.
2. Discussion of Related Art
Bridge circuits are known to connect a first electronic bus to a second electronic bus. The bridge circuit serves to adapt the signals of the two busses to enable data exchange between the two bus signal standards. Frequently, bridge circuits are used to convert between different signaling standards defined for the first and second busses. Another common application of bus bridge circuits, as discussed in the related application Ser. No. 08/673,654 incorporated herein by reference, is to connect multiple, often hierarchical busses to common devices or memory subsystems.
In RAID storage subsystem control applications, for example, a Peripheral Computer Interconnect (PCI) bus is used to connect various peripheral I/O devices through a bridge circuit to a centralized PCI bus for the overall control of all I/O devices in the subsystems as well as the cache memory subsystem. The bus connecting the RAID subsystem CPU to the PCI bus bridge is referred to herein as the primary side or primary I/O bus, and attaches to the primary bus port of the bridge. The bus connected to the bus bridge circuit on the opposite side of the bridge relative to the primary side is referred to herein as the secondary side or secondary I/O bus and connects to the secondary bus port of the bridge. Transactions flowing through the bridge circuit from the primary side to the secondary side are referred to herein as downstream transactions or downstream flow. Transactions flowing through the bridge circuit from the secondary side to the primary side are referred to herein as upstream transactions or upstream flow.
The device initiating or originating the transaction request is known as the initiator or busmaster. The device to which the initiator directs its request is the target. When, for example, a CPU originates a transaction request it is the initiator, that is, busmaster. The target, for example, might be cache or other memory module.
If a read transaction has been performed and more data accesses may be required, data that may be requested is prefetched. The PCI bridge is designed to perform read prefetches from the target faster than necessary, and transfer the data to the initiator in response to future read transactions. This technique is known to enhance read transaction performance.
With regard to PCI bus architecture, read prefetch can be implemented with or without a buffer. When read prefetch is implemented with a buffer, data within data addresses following the current area of memory being read, are stored in a buffer and transferred to the initiator in response to possible future read transactions. Read prefetch with a buffer allows the PCI bus bridge to utilize the PCI burst mode without a lockstep handshake. During burst mode, the PCI bus bridge joins the addresses of these sequential read operations, transfers the beginning address once, and performs the data transfer. Successive addresses of these sequential read operations are not transferred while the data is transferred because they are implied. Thus, the amount of data transferred during burst mode is increased because the bus is not required to transfer each address during the data transfer.
When read prefetch is not implemented with a buffer, PCI bust mode is still utilized, but multiple data addresses cannot be prefetched. Instead, only one data address in the current area of memory being read can be prefetched, stored in a single register, and transferred to the initiator during the next data phase of the current burst. Since there is no buffer space to store the large amount of prefetched data, both sides of the PCI bus bridge are required to be in lockstep. A handshake is required between both sides of the bridge because the bus slave, or target must wait for the bus master to request the next read operation.
If immediate delivery of write data from initiator to target in a write transaction is not necessary, the PCI bridge can temporarily write data to a buffer within the PCI bus bridge before the write data is transferred to the storage medium such as the RAID disk, cache, or non-volatile memory. This is known to enhance write transaction performance because buffering and posting do not require both sides of bridge to be in lock step. That is when buffering data, there is no requirement for a handshake between both sides of the bridge during each data cycle that is transferring data between sides of the bridge. Although the busmaster or initiator is notified data delivery has occurred, data delivery has not actually occurred but will soon afterwards because the data that is left in the buffer is transferred at a later time.
In the downstream direction, it is known in the art to selectively enable memory read prefetch support. Prefetching can be implemented with or without a buffer. In the upstream direction, it is known in the art to globally disable memory prefetch support. Additionally in the downstream or upstream direction, it is known in the art to globally disable memory write buffering or posting. For more information, the reader is directed to PCI Special Interest Group, PCI to PCI Bridge Architecture Specification, Revision 1.0, Apr. 5, 1994, Hillsboro, Oreg., and PCI Special Interest Group, PCI Local Bus Specification, Revision 2.1, Jun. 1, 1995, Portland, Oreg.
In prior PCI bus bridges, upstream read transactions directed to memory target devices may often use prefetch. If the prefetch of upstream read transactions is directed to certain I/O targets that cannot utilize prefetch, it is known in the art, to provide a device specific bit in configuration space that globally disables upstream transaction read prefetch for all upstream read transactions. When upstream transaction read prefetch is globally disabled, read prefetch remains globally disabled for upstream transactions on a PCI bridge even though there may be other targets that allow read prefetch. The prefetch ability remains globally disabled because the prior PCI bus bridge cannot selectively disable read prefetch on upstream transactions. This reduces system performance for upstream transaction memory read commands to prefetchable main memory. A need exists to selectively enable and disable destinations for prefetch of upstream transaction memory read commands.
Additionally, in prior PCI bridges, buffering or posting of all upstream transaction memory write commands must be globally disabled to guarantee immediate delivery of upstream transaction data to certain targets. This reduces system throughput because the system does not utilize buffering or posting of data for other targets that do not need immediate delivery of upstream transaction data. It is desirable to improve system performance by allowing the immediate delivery of upstream transaction data, for certain targets, and allow upstream transaction buffering/posting of memory write commands for other targets.